1. Field of the Invention
The present invention relates to a nonvolatile memory device, and more particularly, to electrically erasable and programmable read only memory (EEPROM) devices having a junction structure that can compensate for the reduction of effective channel length.
2. Description of the Related Art
A nonvolatile memory device is a memory device that maintains stored data in memory cells even if power is removed. Several types of nonvolatile memory devices are available, and an example of a memory device in which data can be programmed and erased electrically is an EEPROM device.
Several types of EEPROM cell structure are known. One example is a memory cell structure containing a selection transistor in series with a memory transistor. The memory transistor can be configured to include a floating gate and a tunnel dielectric (or tunnel oxide) layer.
FIG. 1 is a plan view illustrating the cell structure of a conventional EEPROM device. FIG. 2 is a cross-sectional view of a conventional EEPROM device along a bit line.
In FIGS. 1 and 2, a conventional EEPROM device includes a memory cell composed of a memory transistor 20 on a semiconductor substrate 10 and a selection transistor 30 for selecting the memory transistor 20.
For example, an active region 11 is formed on the semiconductor substrate 10 formed of p-type silicon, and a gate dielectric layer 21 and a tunnel dielectric layer 23 are formed on the active region 11. The tunnel dielectric layer 23 is formed of material such as an oxide layer and is thinner than the gate dielectric layer 21.
A first gate stack 25 and 27 of the memory transistor 20 is formed by sequentially stacking a floating gate 25, an interlayer dielectric layer 29, and a control gate 27 on the tunnel and gate dielectric layers 21 and 23. The floating gates 25 are formed in a floating or a separated island by separating them from each other along a mask pattern 70.
A source region 41 having a lightly doped drain (LDD) is formed on an active region 11 adjacent to the first gate stack 25 and 27. An insulating spacer 51 can be formed on the side wall of the first gate stack 25 and 27 to form the source region 41 in the LDD structure. Junction regions 43 and 45 can be formed on the active region 11 opposite the source region 41. Here, the structure of junction regions 43 and 45 can be understood to be a floating junction region.
As depicted in FIG. 2, a first doped region 43 doped at a relatively high concentration, such as n+, is extended under the tunnel dielectric layer 23 and located on a region opposite the source region 41 facing the n-type source region 41. The first doped region 43 is formed within the region of the first gate stack 25 and 27. As depicted in FIG. 2, a second doped region 45 doped at a relatively low concentration, such as n-typed region, can be formed in the active region 11 exposed to the first gate stack opposite to the source region 41.
The memory transistor 20 may be formed to include the gate dielectric layer 21, the tunnel dielectric layer 23, the floating gate 25, the interlayer dielectric layer 29, the control gate 27, the source region 41, the first doped region 43, and the second doped region 45.
As depicted in FIG. 2, a second gate stack 35 and 37 adjacent to the second doped region 45 of the junction region structure 43 and 45 is formed to connect the memory transistor 20 in series, and a selection transistor 30 that includes an n−type drain region 47 is formed on the active region 11 opposite the second doped region 45. The first gate 35 and the second gate 37 of the selection transistor 30 are formed together corresponding respectively to the floating gate 25 and the control gate 27.
A bit line 65 extending orthogonal to the first and second gates 35 and 37 of the selection transistor 30 which is used as a word line is electrically connected to the drain region 47. The bit line 65 is electrically connected to the drain region 47 via a bit line contact 61 that passes through an insulating layer 55. Also, the control gate 27 of the memory transistor 20 is used as a sensing line.
However, in the conventional EEPROM device depicted in FIGS. 1 and 2, as the memory capacity increases, the size of a unit cell decreases. If the size of the cell is reduced, the cell characteristics degrade. As a result, punch through may harmfully occur. As the size of the cell decreases, the gate length of the memory transistor 20 and/or the selection transistor 30 is reduced, that is, the length of a channel is reduced. Therefore, punch through can occur by connecting the depletion layers of two junctions separated by the gate, such as the source region 41 and the first doped region 43, or the second doped region 45 and the drain region 47.
To solve the punch through problem, a method is provided to compensate for the length reduction of the effective gate channel due to the length reduction of the gate. To compensate for the reduced effective channel length, changing the ion implantation energy condition or ion implantation dose for junctions 41, 43, 45 and 47 may be necessary. However, the conventional junction structures as depicted in FIGS. 1 and 2 simply show that changing the implantation energy or dose of ions has limited effect of compensating for the length reduction of the effective channel length due to the length reduction of the gate.